k3p7v(u)1000b-yc cmos mask rom 64m-bit (8mx8 /4mx16) cmos mask rom the k3p7v(u)1000b-yc is a fully static mask programmable rom fabricated using silicon gate cmos process technology, and is organized either as 8,388,608 x 8 bit(byte mode) or as 4,194,304 x 16 bit(word mode) depending on bhe voltage level.(see mode selection table) this device includes page read mode function, page read mode allows 8 words (or 16 bytes) of data to read fast in the same page, ce and a 3 ~ a 21 should not be changed. this device operates with 3.0v or 3.3v power supply, and all inputs and outputs are ttl compatible. because of its asynchronous operation, it requires no external clock assuring extremely easy operation. it is suitable for use in program memory of microprocessor, and data memory, character generator. the k3p7v(u)1000b-yc is packaged in a 48-tsop1. general description features switchable organization 8,388,608 x 8(byte mode) 4,194,304 x 16(word mode) fast access time random access time/page access time 3.3v operation : 100/30ns(max.)@c l =50pf, 120/40ns(max.)@c l =100pf 3.0v operation : 120/40ns(max.)@c l =100pf 8 words / 16 bytes page access supply voltage : single +3.0v/ single +3.3v current consumption operating : 60ma(max.) standby : 50 m a(max.) fully static operation all inputs and outputs ttl compatible three state outputs package k3p7v(u)1000b-yc : 48-tsop1-1218 a 21 x a 0~ a 2 and decoder buffers a 3 y and decoder buffers memory cell sense amp. control logic matrix (4,194,304x16/ 8,388,608x8) data out buffers a -1 ce oe bhe . . . . . . . . q 0 /q 8 q 7 /q 15 . . . functional block diagram pin name pin function a 0 - a 2 page address inputs a 3 - a 21 address inputs q 0 - q 14 data outputs q 15 /a -1 output 15(word mode)/ lsb address(byte mode) bhe word/byte selection ce chip enable oe output enable v cc power vss ground n.c no connection free datasheet http:///
k3p7v(u)1000b-yc cmos mask rom absolute maximum ratings note : permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to t he conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extend ed periods may affect device reliability. item symbol rating unit voltage on any pin relative to v ss v in -0.3 to +4.5 v temperature under bias t bias -10 to +85 c storage temperature t stg -55 to +150 c recommended operating conditions (voltage reference to v ss , t a =0 to 70 c) item symbol min typ max unit supply voltage v cc 2.7/3.0 3.0/3.3 3.3/3.6 v supply voltage v ss 0 0 0 v pin configuration bhe a 16 a 15 a 14 a 13 a 12 a 11 a 9 a 8 a 10 a 20 a 18 a 17 a 7 a 6 a 5 a 4 k3p7v(u)1000b-yc 1 2 48 47 3 4 5 6 7 8 9 10 39 11 12 37 13 14 15 16 17 18 19 20 21 22 tsop1 a 3 a 1 q 4 23 24 a 0 ce v ss oe q 0 q 8 q 1 q 3 q 9 q 2 q 10 46 45 44 43 42 41 40 38 36 35 34 33 32 31 30 29 28 27 26 25 q 15/ a- 1 q 7 q 14 q 6 q 13 q 5 q 12 q 11 v ss a 2 a 19 v ss v ss n.c v ss v cc v cc v ss v ss a 21 dc characteristics note : minimum dc voltage(v il ) is -0.3v an input pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input pins(v ih ) is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. parameter symbol test conditions min max unit operating current i cc cycle=5mh z , all outputs open, ce = oe =v il , v in =0.45v to 2.4v (ac test condition) v cc =3.3v 0.3v - 60 ma v cc =3.0v 0.3v 50 ma standby current(ttl) i sb1 ce =v ih , all outputs open 500 m a standby current(cmos) i sb2 ce =v cc , all outputs open 50 m a input leakage current i li v in =0 to v cc - 10 m a output leakage current i lo v out =0 to v cc - 10 m a input high voltage, all inputs v ih 2.0 v cc +0.3 v input low voltage, all inputs v il -0.3 0.6 v output high voltage level v oh i oh =-400 m a 2.4 - v output low voltage level v ol i ol =2.1ma - 0.4 v free datasheet http:///
k3p7v(u)1000b-yc cmos mask rom test conditions item value input pulse levels 0.45v to 2.4v input rise and fall times 10ns input and output timing levels 1.5v output loads 1 ttl gate and c l =50pf or 100pf ac characteristics (t a =0 c to +70 c,v cc =3.3v/3.0v 0.3v, unless otherwise noted.) mode selection ce oe bhe q 15 /a -1 mode data power h x x x standby high-z standby l h x x operating high-z active l l h output operating q 0 ~q 15 : dout active l input operating q 0 ~q 7 : dout q 8 ~q 14 : hi-z active capacitance (t a =25 c, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test conditions min max unit output capacitance c out v out =0v - 12 pf input capacitance c in v in =0v - 12 pf read cycle note : page address is determined as below. word mode (bhe=v ih ) : a 0 , a 1, a 2 byte mode (bhe=v il ) : a -1 , a 0 , a 1, a 2 item symbol k3p7v1000b-yc10 (c l =50pf) k3p7v1000b-yc12 (c l =100pf) K3P7U1000B-YC12 (c l =100pf) unit min max min max min max read cycle time t rc 100 120 120 ns chip enable access time t ace 100 120 120 ns address access time t aa 100 120 120 ns page address access time t pa 30 40 40 ns output enable access time t oe 30 40 40 ns output or chip disable to output high-z t df 20 20 20 ns output hold from address change t oh 0 0 0 ns free datasheet http:///
k3p7v(u)1000b-yc cmos mask rom timing diagram read add ce oe d out a 0 ~a 21 a -1(*1) d 0 ~d 7 d 8 ~d 15(*2) page read oe add d out ce add a 0, a 1, a 2 a 3 ~a 21 valid data valid data valid data valid data 1 st 2 nd 3 rd t df(*3) add1 add2 valid data valid data t oh t df(*3) t rc t ace t oe t aa notes : *1.byte mode only. a -1 is least significant bit address.(bhe = v il ) *2. word mode only.(bhe = v ih ) *3. t df is defined as the time at which the outputs achieve the open circuit condition and is not referenced to v oh or v ol level. t aa t pa a -1(*1) d 0 ~d 7 d 8 ~d 15(*2) ? ? ? ? ? ? ? ? free datasheet http:///
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